1. Field
Example embodiments relate to semiconductor structures and methods for manufacturing semiconductor structures.
2. Description of the Related Art
There are many different types of three-dimensional (3D) bonding technologies. These may generally be grouped into three categories. For packages, a wafer may be divided into chips which are then stacked and packaged to form a multi-stacked package. For chips, a wafer may be formed with or without vias, which is then diced into chips and stacked to form a multi-chip package (MCP) or a 3D chip stack package (CSP). For wafers, two or more wafers may be formed with or without vias, stacked, and diced to form a wafer-level 3D chip stack package (WL-3D CSP).
There are advantages and disadvantages of wafer-level 3D bonding at various levels. At the package level and the chip level, advantages may include extendability to current technology, ease of integrating different processes or materials, short-term development, and/or little or no yield loss.
At the wafer level, advantages may include higher performance, higher density, shorter vertical interconnections, and/or lower cost to achieve WL-CSP and/or real chip size.
Conventional techniques for achieving wafer-level 3D bonding may include i) through via formation technology, which may further include via machining and/or void-free via filling, ii) wafer thinning (for example, to ˜50 um), iii) high-accuracy uniform bonding, and/or iv) micro-gap filling technology. The location of each of these technologies is illustrated in FIG. 1.
There are also fabrication challenges for stacked wafers. These may include i) alignment, where better than 1 μm accuracy may be needed and alignment accuracy affected by bow/stress build-up, ii) bonding including bonding strength and defects, adhesive properties and thickness variation control, and/or lower temperature bonding, iii) thinning including thinning uniformity for etch-stop and edge cracking and loss, and iv) higher aspect-ratio through via formation including through via etch using, for example, plasma or laser, via fill including enhanced plasma (EP) or chemical vapor deposition (CVD), and via cleaning.
FIG. 2 illustrates a conventional protruding-type 3d stack structure. As shown, an electrode that protrudes from the surface of a chip and a bonding pad are joined in conventional chip stacking. In such an arrangement, i) there is a risk of a joining defect, which may decrease bonding reliability, ii) stack height increases by as much as a portion of the electrode that protrudes from the surface of a chip, and iii) flux is needed to form such a stack.
FIGS. 3a-3d illustrate a conventional process of forming a conventional protruding-type electrode. As shown in FIG. 3a, the electrode 2 may be formed in a substrate 1 surrounded by an isolation layer 3, which is then backlapped, as shown in FIG. 3b. In FIG. 3c, the substrate 1 is etched away, for example, by spin wet etching, to expose a portion of the isolation layer 3. In FIG. 3d, the isolation layer 3 is etched away, for example, also by spin wet etching, to expose a portion of the electrode 2. A shown in FIG. 3d, the electrode 2 protrudes from the chip.